搜索资源列表
verilog1024point-fft
- verilog编写的1024点的fft快速傅立叶变换代码-verilog prepared 1024 point fft Fast Fourier Transform code
FFT
- VERILOG CODE FOR FLOATING POINT 8 POINT FFT
multi-verilog
- 乘法器。fft。 基2.蝶形运算。旋转因子-Multipliers. fft. Group 2 butterfly. Twiddle factor
FFT
- fft--快速傅里叶变换 用verilog硬件语言编写-fft- fast Fourier transform verilog hardware language
1024-point-FFT-in-verilog.pdf
- 1024 点得快速傅里叶变换算法 FPGA in verilog-1024 point FFT on a FPGA written in verilog
8-fft
- FFT 8 PT RDX 2 USING VERILOG
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
implentation of split radix fft through verilog
- this is a verilog code fro implentation of split radix fft
fft
- fft in verilog code for fpga
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module
rec
- 8点8位的FFT，verilog语言，经过Quartus仿真验证-8 piont 8 bits of FFT, verilog language, through the Quartus simulation
FFT
- 使用Verilog硬件描述语言实现信号处理中的FFT信号的变换-Using Verilog hardware descr iption language conversion signal processing FFT signal
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc
verilog1024fft
- 1024点FFT的verilog语言实现的源程序的代码-1024 fft verilog language workout source program code
FFT
- verilog xilinx IP实现FFT仿真-Verilog xilinx IP implementation FFT simulation
sources_1
- 使用 wtfa pfa方法 混合基搭建 600点fft verilog -Wtfa pfa method using a mixed group to build a 600-point fft verilog
fft
- 快速傅里叶变换用verilog语言写的模块，，可以从中可以得到点思路-Fast Fourier transform verilog module, the experiment is available, you can get some ideas
Nexys4FFTDemo-master
- A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT output
fft512
- 基于verilog IP核的FFT工程，512位FFT运算，(FFT engineering based on Verilog IP kernel and 512 bit FFT operation,)
DDS
- 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)